This invention relates generally to infrared detector arrays and more particularly to infrared detector array structures wherein the array of infrared detectors and associated electronic detector integration/read circuits are formed as a hybrid integrated circuit.
As is known in the art, infrared detectors are used in a wide range of applications. In one application, an array of the detectors are used as sensors to detect the infrared energy emitted by objects in a scene under observation. Each detector generates an electrical charge in response to the portion of the emitted energy it detects. Circuitry is provided for converting the generated charge into a corresponding electrical signal. The electrical signals are combined by a processor which produces a corresponding visual image of the observed scene. Thus, each detector provides the data for a corresponding pixel of the produced visual image.
In one arrangement, an optical system focuses the emitted infrared energy into a corresponding image on the focal plane of the optical system. The infrared detectors are formed as an array of electrically isolated photo-diode detectors along one surface of a semiconductor chip, typically a chip of InSb or HgCdTe. The chip is disposed on the focal plane. Each photo-diode detector in the array generates an electrical current representative of the amount of infrared power focused onto it. The current is integrated by an integration circuit, typically a capacitor during an integration mode, to produce an electrical signal representative of the infrared energy impinging the photo-diode detector. The integrated signal is read out and passed to the processor during a subsequent read mode. Finally, any residual charge generated in the photo-diode detector, as well as the charge built-up on the capacitor, are removed before the next address cycle during a reset mode.
In one arrangement, the integration/read circuit, as well as a reset circuit, is formed as an integrated circuit in a second semiconductor chip, typically Si. More particularly, an array of integration/read circuit, as well as the reset circuits, is arranged in a matrix of rows and columns formed in the second semiconductor chip. Each one of the circuits is disposed in vertical alignment, or registration with, and is electrically connected to, a corresponding one of the photo-diode detectors. Thus, the first and second semiconductor chips are disposed in overlaying parallel planes. This arrangement allows for the direct electrical connection between each photo-diode detector and its associated integration/read circuit, as well as its associated reset circuit. An exemplary one of the circuits is shown in FIG. 1 as circuit 10'.
The exemplary circuit 10' is shown connected to a photo-diode detector 12'. The diode detector 12' is formed in a region 13' of the first semiconductor chip 14', and the circuit 10' is formed in a region 16' of the second semiconductor chip 18'. It is noted that the region 16' of second chip 18' where the circuit 10' is formed in vertical alignment with the region 13' where the diode detector 12' is formed in the first semiconductor chip 14'. The circuit 10' includes five field effect transistors, F.sub.1, F.sub.2, F.sub.3, F.sub.4, and F.sub.5, arranged as shown, and a capacitor C'.sub.int. During all three modes (i.e., the integration mode, the read mode, and the reset mode), a bias voltage, V.sub.bias, is applied to the gate electrode of transistor F.sub.4 to bias such transistor F.sub.4 into conduction, for reasons to be discussed. Further, the circuit 10' is supplied by a drain voltage supply V.sub.dd and a source voltage supply V.sub.ss, as indicated. During the integration mode, transistor F.sub.1 is switched "on" by a set voltage, V.sub.set, fed to the gate electrode thereof, while transistors F.sub.3 and F.sub.2 are switched "off" by V.sub.reset and V.sub.read logic signals fed to the gate electrodes of transistors F.sub.3 and F.sub.2, respectively. Thus, charge generated in the photo-diode detector 12' in response to impinging infrared radiation is fed, via transistors F.sub.1 and F.sub.4, to the capacitor C.sub.int for integration. Therefore, during this integration mode, transistors F.sub.1 and F.sub.4 are in conducting conditions, and transistors F.sub.2 and F.sub.3 are in non-conducting conditions. After a predetermined integration time, transistor F.sub.2 is switched "on". The voltage built-up by capacitor C.sub.int and the gate electrode capacitance of transistor F.sub.5 produces a corresponding voltage on the source electrode of such transistor. When transistor F.sub.2 is switched "on" during the read mode, the voltage on the source electrode of transistor F.sub.5 produces a corresponding voltage on the source electrode of the transistor F.sub.2 which is coupled to an output bus 19'. During the subsequent reset mode, a V.sub.reset logic signal is fed to the gate electrode of transistor F.sub.3 to place such transistor in an "on" condition while the logic signal V.sub.read on the gate electrode of transistor F.sub.2 turns such transistor F.sub.2 to an "off" condition. Therefore, during the reset mode, charge built-up on the capacitor C.sub.int discharges to V.sub.ss through the source and drain electrodes of transistor F.sub.3. Likewise, any charge generated in the photo-diode detector 12' is also discharged to V.sub.ss through the source and drain electrodes of transistors F.sub.1, F.sub.3, and F.sub.4. It is noted that because of the bias on transistor F.sub.4 switching transients coupled through any parasitic gate-drain capacitance of transistor F.sub.3 and remaining channel charge of transistor F.sub.3 (and appearing on the drain of such transistor F.sub.3) is attenuated prior to passing to the diode detector 12'. That is, transistor F.sub.4 acts as a buffer, or isolation device, and attenuates transients resulting from a change in the V.sub.reset logic state of the signal on the gate of transistor F.sub.3 from passing to the diode detector 12'. The voltage on the gate electrode of transistor F.sub.1 is selected to not only place such transistor F.sub.1 in a conducting condition; but, as noted above, is also selected to apply an appropriate reverse bias voltage to the diode detector 12'. Since the circuit 10' is formed in the region 16' of the silicon chip 18' disposed in vertical alignment with the diode detector device 12' connected to it, in order to reduce the amount of spacing between adjacent photo-diode detectors (and thereby increase array resolution), or alternatively, in order to increase the size of the integration capacitor C.sub.int used in the circuit (and thereby increase detection sensitivity), it is desirable to reduce the number of active devices (i.e., transistors) required to implement the circuit 10'.